Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems
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DOI: 10.1109/tcsii.2022.3175066
Abstract: Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device,… read more here.
Keywords: cyclic redundancy; redundancy check; error; sddc decoding ... See more keywords