Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop
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DOI: 10.1109/cjece.2019.2895047
Abstract: It appears that the relentless pursuit of Moore’s law scaling from one generation of process technology to the next increases circuit vulnerability to single-event transient (SET)-induced double-node upset (SEDU). In this paper, we present a… read more here.
Keywords: node upset; sedu hardened; power; flip flop ... See more keywords