CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM
Sign Up to like & getrecommendations! Published in 2020 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2020.113732
Abstract: Abstract Spin-transfer torque (STT)-magnetic random access memory (MRAM) requires yield-aware design for hybrid magnetic-CMOS integration. In this paper, a novel cycle-sensing margin enhancement (CSME) scheme with pMOS assisted voltage-type sense amplifier (p-VSA) is proposed to… read more here.
Keywords: cycle sensing; sensing margin; novel cycle; margin enhancement ... See more keywords
Asymmetric and Double-Layered Gate-All- Around Structures of 1T-DRAM for Sensing Margin and Retention Improvement
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2024.3385394
Abstract: A general dynamic random access memory (DRAM) is consisted of transistor and capacitor and has continuously scaled down the cell size for larger memory density. However, one transistor-DRAM (1T-DRAM) is a promising device, which integrates… read more here.
Keywords: double layered; sensing margin; structure; dram ... See more keywords