A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line
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DOI: 10.1109/jssc.2020.3045168
Abstract: A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the… read more here.
Keywords: quadrature phase; sequential delay; delay control; delay ... See more keywords