Power-effective ROM-less DDFS Design Approach with High SFDR Performance
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Signal Processing Systems"
DOI: 10.1007/s11265-019-01460-x
Abstract: A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based… read more here.
Keywords: design approach; rom less; sfdr; approach ... See more keywords
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2023.3242658
Abstract: This paper presents an approach to the mitigation of harmonic distortions in wideband current-steering digital-to-analog converters (DACs). This approach enables code-independent constant-switching-activity data-weighted-averaging (CSA-DWA) with the extra area and power overhead by exploiting redundant current… read more here.
Keywords: csa dwa; bit; activity; switching activity ... See more keywords