Stacked Assembly of SiC Cascode Using Buried Gate Static Induction Transistor
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2020.3022083
Abstract: A 650-V and 10-A silicon carbide (SiC) stacked cascode assembly has been proposed and demonstrated, in which a low-voltage Si-MOSFET (LV Si-MOSFET) is stacked on a high-voltage SiC buried gate static induction transistor (HV SiC-BGSIT).… read more here.
Keywords: cascode; induction transistor; gate static; static induction ... See more keywords
Comparative Investigation on Paralleling Suitability for SiC MOSFETs and SiC/Si Cascode Devices
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Industrial Electronics"
DOI: 10.1109/tie.2021.3070519
Abstract: Silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) and SiC/Si cascode devices are two popular normally-off SiC power devices. In terms of the rated voltage and current of a single chip, there are always some… read more here.
Keywords: mosfets sic; cascode devices; paralleling suitability; sic mosfets ... See more keywords
Short-Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison With SiC MOSFETs
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Industrial Electronics"
DOI: 10.1109/tie.2021.3099247
Abstract: Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In… read more here.
Keywords: 650 gan; short circuit; cascode devices; cascode ... See more keywords
Unlocking the Full Potential of GaN/SiC Cascode Device With 3D Co-Packaging and Enhanced dv/dt Control Capability
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Transactions on Power Electronics"
DOI: 10.1109/tpel.2025.3530510
Abstract: To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3-D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation. Equipped… read more here.
Keywords: cascode device; gan sic; control; sic cascode ... See more keywords