Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs
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DOI: 10.3390/ma15175995
Abstract: 650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used… read more here.
Keywords: 650 sic; jfet; gate oxide; sic planar ... See more keywords