Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction
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DOI: 10.1109/ted.2019.2898328
Abstract: Vertical tunneling FET utilizing hetero-line architecture with GeSn/SiGeSn staggered tunneling junction (TJ) is designed and theoretically characterized. Utilizing vertical spacer etching and selective growth techniques, p+ GeSn source/n+ SiGeSn pockets line tunneling can be realized,… read more here.
Keywords: staggered tunneling; sigesn; hetero line; line ... See more keywords