Power-aware sourse feedback single-ended 7T SRAM cell at nanoscale regime
Sign Up to like & getrecommendations! Published in 2019 at "Microsystem Technologies"
DOI: 10.1007/s00542-017-3570-y
Abstract: This article presents a low power and highly stable source feedback SE7T (single-ended 7T) SRAM cell. Using Monte-Carlo simulations critical design metrics of proposed SE7T SRAM cell are estimated and the estimated results are compared… read more here.
Keywords: single ended; power; feedback; sram cell ... See more keywords
High-selectivity single-ended and balanced bandpass filters using ring resonators and coupled lines loaded with multiple stubs
Sign Up to like & getrecommendations! Published in 2018 at "AEU - International Journal of Electronics and Communications"
DOI: 10.1016/j.aeue.2018.09.021
Abstract: Abstract High-selectivity single-ended and balanced bandpass filters (BPFs) using dual-mode ring resonators and coupled lines loaded with multiple stubs are proposed in this paper. With the help of the loaded short-circuited and open-circuited stubs, six… read more here.
Keywords: balanced bandpass; high selectivity; ended balanced; bandpass filters ... See more keywords
Single-ended MMC-MTDC line protection based on dual-frequency amplitude ratio of traveling wave
Sign Up to like & getrecommendations! Published in 2020 at "Electric Power Systems Research"
DOI: 10.1016/j.epsr.2020.106808
Abstract: Abstract Fast and reliable DC line protection is an essential challenge for the modular multilevel converter (MMC) based multi-terminal direct current (MTDC) grid. This paper proposed a novel single-ended protection scheme for DC lines in… read more here.
Keywords: protection; mmc mtdc; frequency; single ended ... See more keywords
A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications
Sign Up to like & getrecommendations! Published in 2021 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/abf7d3
Abstract: In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed… read more here.
Keywords: sram array; power; single ended; array single ... See more keywords
A 32 nm single-ended single-port 7T static random access memory for low power utilization
Sign Up to like & getrecommendations! Published in 2021 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/ac07c8
Abstract: In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise… read more here.
Keywords: random access; static random; access memory; single ended ... See more keywords
A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3206014
Abstract: For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode… read more here.
Keywords: topology; based otas; inverter based; single ended ... See more keywords
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2883395
Abstract: The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a… read more here.
Keywords: dram per; per bit; gddr6 dram; single ended ... See more keywords
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2020.3006864
Abstract: A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin… read more here.
Keywords: single ended; pam transceiver; pam; memory ... See more keywords
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3104093
Abstract: Demand for dynamic random access memory (DRAM) bandwidth has outpaced DRAM transistor performance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6 with costly high bandwidth memory… read more here.
Keywords: pam; gddr6x dram; single ended; achieving pin ... See more keywords
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3147467
Abstract: We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify… read more here.
Keywords: cmos; 128 single; finfet cmos; inline formula ... See more keywords
A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3163284
Abstract: This article presents a highly digital robust voltage-controlled oscillator (VCO)-based front end for multiplexed single-ended resistive sensor readout applications. The architecture features a modified digital phase-locked loop (DPLL) structure that enables second-order noise shaping without… read more here.
Keywords: multiplexed single; vco; single ended; readout ... See more keywords