60 pW 20 μm size CMOS implementation of an actual soma membrane
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DOI: 10.1007/s10825-019-01431-2
Abstract: The article presents a 65 nm technology implementation of a low-power artificial spiking neuron intellectual property (IP) core. The concept of the circuit is based on modeling the mechanism of a perikaryon membrane and the… read more here.
Keywords: size cmos; implementation; mode power; power ... See more keywords