A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2017.2771811
Abstract: This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch… read more here.
Keywords: sar adc; time skew; sndr sar; time ... See more keywords
A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2019.2912887
Abstract: This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs… read more here.
Keywords: background calibrated; sndr sar; coarse comparators; adc ... See more keywords