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Published in 2021 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2020.2987890
Abstract: The estimation of the frequency of the elements on a set is needed in a wide range of computing applications. For example, to estimate the number of hits that a video gets or the number…
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Keywords:
number;
memory;
soft error;
count min ... See more keywords
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Published in 2018 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2017.2748019
Abstract: Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error…
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Keywords:
tcam;
bit;
soft error;
tex math ... See more keywords
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Published in 2020 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2883990
Abstract: Heterogeneous multiprocessor systems on a chips (MPSoCs) consisting of cores with different performance/power characteristics are widely used in many real-time embedded systems, where both soft-error reliability and lifetime reliability are key concerns. Although existing efforts…
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Keywords:
time;
real time;
soft error;
time systems ... See more keywords
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Published in 2019 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2883993
Abstract: Multiprocessor system-on-chip (MPSoC) has been widely used in many real-time embedded systems where both soft-error reliability (SER) and lifetime reliability (LTR) are key concerns. Many existing works have investigated them, but they focus either on…
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Keywords:
real time;
soft error;
time mpsocs;
lifetime reliability ... See more keywords
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Published in 2021 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3085516
Abstract: With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space…
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Keywords:
error immune;
immune read;
read stability;
soft error ... See more keywords
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Published in 2021 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3097981
Abstract: Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital…
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Keywords:
deep neural;
neural networks;
soft error;
reliability ... See more keywords
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Published in 2020 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2020.3025727
Abstract: Problems caused by neutron-induced soft errors in electrical devices are becoming increasingly common in various applications. The neutron-energy-dependent soft-error rate is indispensable for evaluating the frequency of such errors in different neutron fields. We have…
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Keywords:
soft error;
error rate;
error;
energy ... See more keywords
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Published in 2021 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2021.3064666
Abstract: Neutrons with energies between 0.1 and 10 MeV can significantly impact the soft error rate (SER) in SRAMs manufactured in scaled technologies, with respect to high-energy neutrons. Their contribution is evaluated in accelerator, ground-level, and…
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Keywords:
rate accelerator;
error rate;
soft error;
rate ... See more keywords
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Published in 2021 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2021.3070856
Abstract: Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable…
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Keywords:
soft error;
error reliability;
error;
sram based ... See more keywords
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Published in 2021 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2021.3075176
Abstract: We found that specific pairs of pMOS and nMOS transistors in dual interlocked storage cell flip flop (DICEFF) become sensitive to soft errors by device simulations. We propose several layout structures that can improve soft-error…
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Keywords:
tex math;
inline formula;
error tolerance;
soft error ... See more keywords
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Published in 2017 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2016.2569562
Abstract: Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing methodology to reduce the soft error rate (SER) of combinational…
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Keywords:
reduction;
methodology;
gate;
error rate ... See more keywords