A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3163819
Abstract: This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on… read more here.
Keywords: mhz; discrete time; split source; delta sigma ... See more keywords
Multidimensional Pulsewidth Modulation for Cascaded Split-Source Inverter
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Industrial Electronics"
DOI: 10.1109/tie.2022.3150087
Abstract: Cascaded split-source inverter (CSSI) is a single-stage modular multilevel structure. This article proposes the multidimensional pulsewidth modulation (MD-PWM) for this topology. All multilevel modulations are a particular version of this approach. The principles of this… read more here.
Keywords: topology; split source; pulsewidth modulation; cascaded split ... See more keywords