LAUSR

About LAUSR
Donate
Contact Us

Follow us:

You are not signed in:

Sign Up!


   Articles with "sram" as a keyword



Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell

Sign Up to like & get
recommendations! Published in 2017 at "Wireless Personal Communications"

DOI: 10.1007/s11277-017-4226-z

Abstract: Rapid increase in technology is showing a great perception in assessing the complexity of design that can be integrated on a single chip dramatically. Minimum feature sizes, low power consumption, minimum cost and high performance… read more here.

Keywords: array; sram; sram cell; low power ... See more keywords

Dependency of well-contact density on MCUs in 65-nm bulk CMOS SRAM

Sign Up to like & get
recommendations! Published in 2017 at "Science China Information Sciences"

DOI: 10.1007/s11432-017-9549-8

Abstract: Dear editor, In custom static random access memory (SRAM) cell, radiation-induced single bit upsets (SBUs) are considered as the main cause of soft error [1]. Advanced technologies and scaling down of feature sizes have made… read more here.

Keywords: mcu; well contact; density; sram ... See more keywords

A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array

Sign Up to like & get
recommendations! Published in 2018 at "Solid-state Electronics"

DOI: 10.1016/j.sse.2018.07.005

Abstract: Abstract The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute for high data reliability. But the single ended nature of read operation demands a complete Vdd swing of high capacitive… read more here.

Keywords: technique; energy; assist technique; sram ... See more keywords

Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors

Sign Up to like & get
recommendations! Published in 2025 at "Nature Communications"

DOI: 10.1038/s41467-025-59993-8

Abstract: Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed performance and low power consumption. However, scaling SRAM cells to advanced technology… read more here.

Keywords: sram cells; integration; memory; sram ... See more keywords

Design of an enhanced write stability, high-performance, low power 11T SRAM cell

Sign Up to like & get
recommendations! Published in 2021 at "International Journal of Electronics"

DOI: 10.1080/00207217.2020.1870738

Abstract: In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which imp... read more here.

Keywords: sram; sram cell; performance; design enhanced ... See more keywords

Cache performance of NV-STT-MRAM with scale effect and comparison with SRAM

Sign Up to like & get
recommendations! Published in 2021 at "International Journal of Electronics"

DOI: 10.1080/00207217.2021.1908630

Abstract: ABSTRACT Cache is the bridge between CPU and memory for data exchange, which consumes up to 45% of the entire CPU energy. Low power cache and memory are urgently required for the computer system. The… read more here.

Keywords: sram; cache; performance; stt mram ... See more keywords

Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm

Sign Up to like & get
recommendations! Published in 2019 at "IETE Journal of Research"

DOI: 10.1080/03772063.2017.1393351

Abstract: ABSTRACT The quest for low power increases with the advancement in technology as a result of continuous device scaling. Static random access memory (SRAM) represents the technology workhorse due to its compatibility with the logic.… read more here.

Keywords: analysis; sram; process; retention voltage ... See more keywords

Hybrid PNN-PPN 10 T SRAM and LCTS for Leakage Reduction in VLSI

Sign Up to like & get
recommendations! Published in 2025 at "IETE Journal of Research"

DOI: 10.1080/03772063.2025.2524485

Abstract: scale integration (VLSI). Leakage power, defined as the unwanted current flow when a transistor is in the OFF state, significantly impacts the power consumption and performance of VLSI designs, particularly during standby modes. Existing methods… read more here.

Keywords: leakage; pnn ppn; hybrid pnn; sram ... See more keywords

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

Sign Up to like & get
recommendations! Published in 2024 at "Physica Scripta"

DOI: 10.1088/1402-4896/ad5ecb

Abstract: This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox,… read more here.

Keywords: sram; inverter sram; noise margin; sram cell ... See more keywords

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Sign Up to like & get
recommendations! Published in 2024 at "Physica Scripta"

DOI: 10.1088/1402-4896/ad61ca

Abstract: Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based… read more here.

Keywords: low power; high speed; sram; sram cell ... See more keywords

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Sign Up to like & get
recommendations! Published in 2024 at "Physica Scripta"

DOI: 10.1088/1402-4896/ad69e8

Abstract: To meet industry requirements of higher transistor count SRAM cells this paper is proposing, a nine-transistor configuration static random access memory (SRAM) cell which is accessible by dual bit line and performing simultaneous read and… read more here.

Keywords: sram; performance; cell; sram cell ... See more keywords