A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications
Sign Up to like & getrecommendations! Published in 2021 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/abf7d3
Abstract: In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed… read more here.
Keywords: sram array; power; single ended; array single ... See more keywords
An in-Array Build-In Self-Test Scheme for Embedded SRAM Array
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2024.3375637
Abstract: An in-array Build-In Self-Test (BIST) scheme is proposed for the embedded SRAM array. The linear feedback shift register (LFSR) is used to implement the pattern generator, and the single/multiple-input signature register (SISR/MISR) is used to… read more here.
Keywords: scheme; build self; self test; array build ... See more keywords