Dynamic heavy ions SEE testing of NanoXplore radiation hardened SRAM-based FPGA: Reliability-performance analysis
Sign Up to like & getrecommendations! Published in 2019 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2019.113437
Abstract: Abstract NanoXplore is the European pioneer vendor to develop ITAR-free radiation-hardened SRAM-based FPGAs. This work is the first to explore dynamic SEE tests in the NG-Medium FPGA device. The reliability-performance analysis of an embedded unmitigated… read more here.
Keywords: radiation hardened; hardened sram; sram based; performance ... See more keywords
Measurement of Radiation Absorbed Dose Effects in SRAM-Based FPGAs
Sign Up to like & getrecommendations! Published in 2020 at "Iete Journal of Research"
DOI: 10.1080/03772063.2020.1768159
Abstract: As of now, SRAM-based FPGAs are mainly preferred in the non-safety applications of NPPs. If the susceptibility to radiation effects of SRAM-FPGAs improves further, then the reliability of the appli... read more here.
Keywords: measurement radiation; based fpgas; sram based; radiation absorbed ... See more keywords
Proton-induced radiation effects in the I/O blocks of an SRAM-based FPGA
Sign Up to like & getrecommendations! Published in 2019 at "Journal of Instrumentation"
DOI: 10.1088/1748-0221/14/10/t10001
Abstract: This work presents an experimental study of the proton-induced failures in the Input/Output blocks and in the associated configuration of an SRAM-based Field Programmable Gate Array (FPGA) using a single inverter ring oscillator-configuration. The tests… read more here.
Keywords: cm2 device; proton induced; radiation effects; induced radiation ... See more keywords
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3153359
Abstract: This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional… read more here.
Keywords: structure; area; based puf; sram based ... See more keywords
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2018.2792445
Abstract: Soft errors are an important issue for SRAM-based Field Programmable Gate Arrays (FPGAs), since they result in permanent alterations of the mapped circuit when they affect their configuration memory. Concurrent Error Detection (CED) techniques, such… read more here.
Keywords: concurrent error; detection; error; fast fourier ... See more keywords
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2017.2717490
Abstract: Compared with application specific integrated circuits (ASICs), static random access memory (SRAM)-based field programmable gate arrays (FPGAs) respond differently to radiation due to the configuration memory vulnerability. In this brief, the differences between the permanent… read more here.
Keywords: based fpgas; error; fault injection; sram based ... See more keywords
Preselection Methods to Achieve Very Low BER in SRAM-Based PUFs—A Tutorial
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3170460
Abstract: The most prevalent industrial PUFs (physical unclonable functions) utilize SRAM-based designs. Bit stability is one of the fundamental problems in PUF design. PUF circuits, which rely on silicon manufacturing mismatches to produce a random key,… read more here.
Keywords: preselection methods; based pufs; methods achieve; tutorial preselection ... See more keywords
A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3224049
Abstract: In this brief, an ADC-free SRAM-based IMC macro is proposed, which enables energy-efficient and high-precision MAC operation by brain-inspired computing. We identify two key features that support IMC macro to achieve high energy efficiency and… read more here.
Keywords: high precision; imc macro; precision mac; sram based ... See more keywords
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Emerging Topics in Computing"
DOI: 10.1109/tetc.2021.3108556
Abstract: To reduce the oversampling rate of baseband signals, decimation is widely used in digital communication systems. Polyphase filters (PPFs) can be used to efficiently implement decimators. SRAM-based FPGAs provide large amounts of resources combined with… read more here.
Keywords: based fpga; fault; decimators sram; polyphase filters ... See more keywords
Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Nanotechnology"
DOI: 10.1109/tnano.2019.2925872
Abstract: A Viterbi decoder is used in many communication receivers to efficiently decode the received signal that has been convolutional encoded in the transmitter. This decoding corrects errors that occur due to noise and other imperfections… read more here.
Keywords: configuration memory; viterbi decoders; sram based; based fpgas ... See more keywords
Delay Monitor Circuit and Delay Change Measurement Due to SEU in SRAM-Based FPGA
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2018.2828785
Abstract: This paper presents a monitor circuit designed for the detection of extra combinational delays in a high-frequency SRAM-based field-programmable gate array (FPGA). Since in most of the SRAM-based FPGAs, more than 90% of the configuration… read more here.
Keywords: monitor circuit; delay; sram based;