A low-power single ended half-select free 7 T SRAM cell with improved write margin at 32 nm technology node
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DOI: 10.1088/1402-4896/ad96f3
Abstract: A single-ended single port 7T SRAM bit-cell with a process-variation tolerant architecture and half-select resilience at 32 nm CMOS technology node is presented. The proposed 7 T (7TP) SRAM bit-cell integrates a low threshold voltage… read more here.
Keywords: single ended; sram bit; cell; margin ... See more keywords