Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors
Sign Up to like & getrecommendations! Published in 2025 at "Nature Communications"
DOI: 10.1038/s41467-025-59993-8
Abstract: Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed performance and low power consumption. However, scaling SRAM cells to advanced technology… read more here.
Keywords: sram cells; integration; memory; sram ... See more keywords
Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Journal of the Electron Devices Society"
DOI: 10.1109/jeds.2025.3531432
Abstract: As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping… read more here.
Keywords: doping engineering; sram cells; performance; drain ... See more keywords
A 7T Security Oriented SRAM Bitcell
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2018.2886175
Abstract: Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented… read more here.
Keywords: oriented sram; sram cells; sram bitcell; security ... See more keywords
Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Device and Materials Reliability"
DOI: 10.1109/tdmr.2024.3417961
Abstract: The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve… read more here.
Keywords: formula tex; sram cells; tex math; inline formula ... See more keywords
Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2945533
Abstract: We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling… read more here.
Keywords: sram cells; carbon nanotube; 10t sram; kbit ... See more keywords