XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2019.2963616
Abstract: We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which… read more here.
Keywords: memory computing; ternary deep; sram macro; xnor sram ... See more keywords
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2023.3240303
Abstract: This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM) macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write ports of the employed 8T SRAM bit-cell eliminate read disturbance during search… read more here.
Keywords: scim reconfigurable; bit parallel; bit; sram macro ... See more keywords
An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2021.3132063
Abstract: In-Memory Computing (IMC) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Recently proposed IMC circuit topologies dramatically reduce data transfer requirements by performing various operations such as Multiply-Accumulate (MAC) inside… read more here.
Keywords: neural network; augmented neural; memory augmented; sram macro ... See more keywords