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Published in 2020 at "Heliyon"
DOI: 10.1016/j.heliyon.2020.e04168
Abstract: In the most advanced technology nodes, leakage has become a major concern for integrated circuits designers. In addition, the leakage calculation using SPICE simulations takes a large amount of time for the entire library of…
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Keywords:
standard cell;
methodology;
leakage;
cell library ... See more keywords
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Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3156890
Abstract: This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a…
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Keywords:
cell;
analog;
standard cell;
design ... See more keywords
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Published in 2019 at "IEEE Transactions on Consumer Electronics"
DOI: 10.1109/tce.2018.2890616
Abstract: Intellectual property protection techniques face a challenging task in countering a physical attack by reverse engineering the netlist of an embedded integrated circuit. An attacker can extract sensitive information with image tools by processing microphotographs…
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Keywords:
reverse engineering;
obfuscation;
standard cell;
reverse ... See more keywords
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Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3199250
Abstract: In this brief we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, NOR…
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Keywords:
cell;
analog;
standard cell;
inline formula ... See more keywords
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Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3212123
Abstract: With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Aging-aware standard cell library is necessary for robust circuit design. To consider aging effects in standard cell libraries, existing methods…
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Keywords:
sensitivity analysis;
cell library;
standard cell;
aging aware ... See more keywords
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Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3151500
Abstract: In this brief, a standard cell library targeting ultra-low voltages (ULVs) is designed in a 65-nm low-power CMOS technology to enable digital integrated circuits (ICs) to achieve good tradeoff among speed, power consumption, area, and…
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Keywords:
standard cell;
cell library;
power;
near subthreshold ... See more keywords
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Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3229442
Abstract: Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this…
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Keywords:
cell library;
impact;
power;
standard ... See more keywords
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Published in 2023 at "Antioxidants"
DOI: 10.3390/antiox12030709
Abstract: Honeybee nests constructed without man-made wax foundation have significantly more variability of cell widths/sizes than those in commercially-kept colonies. The effects of this natural variability in comb cell widths on individual and colony traits have…
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Keywords:
cell;
cell combs;
antioxidant capacity;
small cell ... See more keywords