A Simulation-Guided Paradigm for Logic Synthesis and Verification
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DOI: 10.1109/tcad.2021.3108704
Abstract: This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization and verification algorithms,… read more here.
Keywords: logic synthesis; synthesis verification; simulation guided; simulation ... See more keywords