On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
Sign Up to like & getrecommendations! Published in 2018 at "Genetic Programming and Evolvable Machines"
DOI: 10.1007/s10710-018-9340-5
Abstract: Evolvable hardware allows the generation of circuits that are adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact,… read more here.
Keywords: genetic programming; cartesian genetic; evolvable hardware; array cartesian ... See more keywords
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2020.3048829
Abstract: High accuracy and ever-increasing computing power have made deep neural networks (DNNs) the algorithm of choice for various machine learning, computer vision, and image processing applications across the computing spectrum. To this end, Google developed… read more here.
Keywords: array; toward functional; systolic array; safety systolic ... See more keywords
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3170233
Abstract: Deep learning applications have become ubiquitous in today’s era and it has led to vast development in machine learning (ML) accelerators. Systolic arrays have been a primary part of ML accelerator architecture. To fully leverage… read more here.
Keywords: factored systolic; hybrid accumulator; machine learning; systolic array ... See more keywords