Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Computational Electronics"
DOI: 10.1007/s10825-019-01440-1
Abstract: In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic,… read more here.
Keywords: gotfet; gate overlap; overlap tunnel; technology node ... See more keywords
Perpendicular STT_RAM cell in 8 nm technology node using Co1/Ni3(1 1 1)||Gr2||Co1/Ni3(1 1 1) structure as magnetic tunnel junction
Sign Up to like & getrecommendations! Published in 2018 at "Journal of Magnetism and Magnetic Materials"
DOI: 10.1016/j.jmmm.2017.12.021
Abstract: Abstract The perpendicular anisotropy Spin-Transfer Torque Random Access Memory (P-STT-RAM) is considered to be a promising candidate for high-density memories. Many distinct advantages of Perpendicular Magnetic Tunnel Junction (P-MTJ) compared to the conventional in-plane MTJ… read more here.
Keywords: co1 ni3; technology; stt ram; technology node ... See more keywords
A review on performance comparison of advanced MOSFET structures below 45 nm technology node
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Semiconductors"
DOI: 10.1088/1674-4926/41/6/061401
Abstract: CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of… read more here.
Keywords: mosfet; mosfet structures; channel; technology node ... See more keywords
Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2016.2636338
Abstract: Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers… read more here.
Keywords: pdsoi; technology; single event; technology node ... See more keywords
Anamorphic objective design for extreme ultraviolet lithography at the 5∼1 nm technology node.
Sign Up to like & getrecommendations! Published in 2021 at "Applied optics"
DOI: 10.1364/ao.428136
Abstract: Extreme ultraviolet lithography (EUVL) has been applied in integrated circuit manufacture at the 9-7 nm technology node, in which the numerical aperture (NA) of the objective is 0.33, and the reduction of the objective is… read more here.
Keywords: ultraviolet lithography; lithography; technology node; extreme ultraviolet ... See more keywords