Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
Sign Up to like & getrecommendations! Published in 2017 at "Scientific Reports"
DOI: 10.1038/s41598-017-04055-3
Abstract: Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering… read more here.
Keywords: material based; technology nodes; material; based fets ... See more keywords
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2017.2681064
Abstract: Monolithic 3-D ICs (M3-D ICs) offer extremely high vertical interconnection density, significantly improving the power-performance envelope when compared to conventional 2-D ICs. However, process limitations lead to one tier having either degraded transistors or interconnects.… read more here.
Keywords: degradation; power performance; technology nodes;
Modeling of Via Resistance for Advanced Technology Nodes
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2017.2687524
Abstract: We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the… read more here.
Keywords: self aligned; technology nodes; wire; via resistance ... See more keywords