Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic
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DOI: 10.1109/tcsi.2022.3151920
Abstract: This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the… read more here.
Keywords: low variance; variance memristor; combinational logic; memristor ... See more keywords