SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3147100
Abstract: Test-point insertion (TPI) is an effective technique for improving the random pattern testability of digital circuits. However, it introduces area and performance overhead. Because the test-point area takes a significant portion of the test logic… read more here.
Keywords: test point; point insertion; area; shared point ... See more keywords
Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2017.2704104
Abstract: Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but… read more here.
Keywords: test point; area; test points; coverage ... See more keywords