Efficient balance technique for brain-computer interface applications based on I/Q down converter and time interleaved ADCs
Sign Up to like & getrecommendations! Published in 2020 at "Informatics in Medicine Unlocked"
DOI: 10.1016/j.imu.2019.100276
Abstract: Abstract With the widespread of Internet of things, varied innovative tools are required to control the nearby smart devices. In this contest, brain-computer interface (BCI) technology can empower individuals to directly control varied electronic devices… read more here.
Keywords: computer interface; time interleaved; converter time; brain ... See more keywords
Simultaneous Time Interleaved MultiSlice (STIMS) for Rapid Susceptibility Weighted acquisition
Sign Up to like & getrecommendations! Published in 2017 at "NeuroImage"
DOI: 10.1016/j.neuroimage.2017.04.036
Abstract: ABSTRACT T2* weighted 3D Gradient Echo (GRE) acquisition is the main sequence used for Susceptibility Weighted Imaging (SWI) and Quantitative Susceptibility Mapping (QSM). These applications require a long echo time (TE) to build up phase… read more here.
Keywords: time; susceptibility weighted; time interleaved; acquisition ... See more keywords
Design of a very low power 12 bits, 40 MS/s ADC based on a time-interleaved SAR architecture
Sign Up to like & getrecommendations! Published in 2024 at "Journal of Instrumentation"
DOI: 10.1088/1748-0221/19/05/c05033
Abstract: The paper describes a new figure of merit reachable in terms of very low power dissipation for a 12 bit, 40 MS/s Analog to Digital Converter in a 65 nm CMOS process with 1 V… read more here.
Keywords: architecture; design low; time interleaved; low power ... See more keywords
A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Access"
DOI: 10.1109/access.2024.3381037
Abstract: A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock… read more here.
Keywords: successive approximation; time interleaved; pipelined asynchronous; bit ... See more keywords
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2016.2632300
Abstract: A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid… read more here.
Keywords: adc; pam4 wireline; time; time interleaved ... See more keywords
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2020.3024261
Abstract: A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based… read more here.
Keywords: time interleaved; front end; inverter based; way time ... See more keywords
Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3192546
Abstract: Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path,… read more here.
Keywords: emitter followers; sampling rates; switched emitter; front end ... See more keywords
A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive N-Path Filters
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2024.3394257
Abstract: This work presents a sixth-order partially time-interleaved bandpass delta-sigma modulator (BP DSM) for direct intermediate-frequency (IF) digitization. There are three resonators, and each of them is built with a passive N-path filter; while two open-loop… read more here.
Keywords: passive path; partially time; interleaved bandpass; time interleaved ... See more keywords
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2024.3482567
Abstract: This article presents a 12-GS/s 12-bit $4{\times }$ time-interleaved (TI) pipelined analog-to-digital converter (ADC), which utilizes a global dither injection (GDI) scheme to facilitate an input-independent background timing skew calibration. The GDI scheme adds dithers… read more here.
Keywords: dither; input; dither injection; time interleaved ... See more keywords
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2025.3618188
Abstract: This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( $8 \times 8$ ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the… read more here.
Keywords: discrete multitone; time; time interleaved; 112 discrete ... See more keywords
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Microwave and Wireless Components Letters"
DOI: 10.1109/lmwc.2017.2735548
Abstract: A time-interleaved duobinary transmitter featuring four-way data retiming and a simplified latch + D flip-flop topology to improve the power efficiency and opening of the data eye is reported. A modified bridged shunt-peaking load using… read more here.
Keywords: time interleaved; transmitter achieving; duobinary transmitter; interleaved duobinary ... See more keywords