Efficient balance technique for brain-computer interface applications based on I/Q down converter and time interleaved ADCs
Sign Up to like & getrecommendations! Published in 2020 at "Informatics in Medicine Unlocked"
DOI: 10.1016/j.imu.2019.100276
Abstract: Abstract With the widespread of Internet of things, varied innovative tools are required to control the nearby smart devices. In this contest, brain-computer interface (BCI) technology can empower individuals to directly control varied electronic devices… read more here.
Keywords: computer interface; time interleaved; converter time; brain ... See more keywords
Simultaneous Time Interleaved MultiSlice (STIMS) for Rapid Susceptibility Weighted acquisition
Sign Up to like & getrecommendations! Published in 2017 at "NeuroImage"
DOI: 10.1016/j.neuroimage.2017.04.036
Abstract: ABSTRACT T2* weighted 3D Gradient Echo (GRE) acquisition is the main sequence used for Susceptibility Weighted Imaging (SWI) and Quantitative Susceptibility Mapping (QSM). These applications require a long echo time (TE) to build up phase… read more here.
Keywords: time; susceptibility weighted; time interleaved; acquisition ... See more keywords
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2016.2632300
Abstract: A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid… read more here.
Keywords: adc; pam4 wireline; time; time interleaved ... See more keywords
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2020.3024261
Abstract: A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based… read more here.
Keywords: time interleaved; front end; inverter based; way time ... See more keywords
Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3192546
Abstract: Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path,… read more here.
Keywords: emitter followers; sampling rates; switched emitter; front end ... See more keywords
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Microwave and Wireless Components Letters"
DOI: 10.1109/lmwc.2017.2735548
Abstract: A time-interleaved duobinary transmitter featuring four-way data retiming and a simplified latch + D flip-flop topology to improve the power efficiency and opening of the data eye is reported. A modified bridged shunt-peaking load using… read more here.
Keywords: time interleaved; transmitter achieving; duobinary transmitter; interleaved duobinary ... See more keywords
An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2019.2901795
Abstract: An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The architecture avoids the use of sampling buffers in order to minimize the number of noise sources on… read more here.
Keywords: time interleaved; architecture time; energy efficient; sar adc ... See more keywords
Coding Efficiency Enhancement Using Time Interleaved Level Splitting and Optimized Multi-Level Delta Sigma Modulation in Digital Transmitter
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3077000
Abstract: This paper proposes a novel scheme for energy-efficient transmitter design using optimized multi-level DSM (OML-DSM) along with time-interleaved level splitting technique. This scheme significantly improves the overall transmitter efficiency by providing high coding efficiency (CE)… read more here.
Keywords: interleaved level; time interleaved; level; optimized multi ... See more keywords
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3114708
Abstract: This paper presents signal-independent background calibration for timing errors in time-interleaved ADCs, using a random ramp-based calibration signal. A prototype 10-b 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the… read more here.
Keywords: signal independent; timing calibration; calibration; time interleaved ... See more keywords
Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2019.2956101
Abstract: This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can… read more here.
Keywords: time interleaved; time; time skew; random sampling ... See more keywords
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3160736
Abstract: This brief presents an overview of recent background timing mismatch calibration techniques in time-interleaved ADCs. Regarding the methods of detecting timing skew, the brief divides the existing methods into two categories: a) strategies based on… read more here.
Keywords: calibration techniques; background timing; mismatch calibration; interleaved adcs ... See more keywords