Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2019.2956101
Abstract: This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can… read more here.
Keywords: time interleaved; time; time skew; random sampling ... See more keywords
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2017.2771811
Abstract: This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch… read more here.
Keywords: sar adc; time skew; sndr sar; time ... See more keywords