Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss
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DOI: 10.1109/jssc.2022.3220525
Abstract: Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from miss detection risk due to inactivation of the critical paths. We propose a negative margin timing error… read more here.
Keywords: error detection; timing error; timing margin; detection ... See more keywords