Low Power QC-LDPC Decoder Based on Token Ring Architecture
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DOI: 10.3390/en13236310
Abstract: The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The… read more here.
Keywords: ldpc decoder; low power; token ring; architecture ... See more keywords