A fault-tolerant and congestion-aware architecture for wireless networks-on-chip
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DOI: 10.1007/s11276-019-01962-3
Abstract: The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone… read more here.
Keywords: fault tolerant; tolerant congestion; chip; wireless networks ... See more keywords