Multiple Node Upset-Tolerant Latch Design
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DOI: 10.1109/tdmr.2019.2912811
Abstract: This paper proposes a general method for the design of multiple node upset (MNU)-tolerant latches. First, two double node upset (DNU)-tolerant latches and one triple node upset (TNU)-tolerant latch are introduced. These proposed latches are… read more here.
Keywords: tolerant latch; node upset; multiple node; design multiple ... See more keywords
Radiation Hardened Latch Designs for Double and Triple Node Upsets
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DOI: 10.1109/tetc.2017.2776285
Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,… read more here.
Keywords: dnu tolerant; tolerant latch; triple node; node upsets ... See more keywords
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments
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DOI: 10.1109/tetc.2020.3025584
Abstract: With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely… read more here.
Keywords: tolerant latch; quadruple node; node upsets; node upset ... See more keywords