Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement
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DOI: 10.1109/access.2022.3144981
Abstract: Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct… read more here.
Keywords: ternary inverter; transistor sizing; noise; noise margin ... See more keywords