Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3144981
Abstract: Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct… read more here.
Keywords: ternary inverter; transistor sizing; noise; noise margin ... See more keywords
High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2025.3571482
Abstract: We propose a technique able to reduce nonlinearity in multiplexer-based digital delay interpolators, by optimizing transistor sizing. In our approach, we adjust the driving capabilities of each MOSFET within multiplexers to minimize the interpolation error,… read more here.
Keywords: delay interpolators; transistor sizing; digital delay; based digital ... See more keywords