Comparison of the performance improvement for the two novel SOI-tunnel FETs with the lateral dual-gate and triple-gate
Sign Up to like & getrecommendations! Published in 2018 at "Microsystem Technologies"
DOI: 10.1007/s00542-018-4018-8
Abstract: In this paper, we present two silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), referred as a lateral dual-gate TFET and a lateral triple-gate TFET, which consist of one or two vertical thin vertical dielectric layers within the original front-gate… read more here.
Keywords: gate tfet; triple gate; gate; gate triple ... See more keywords
3-D Analytical Modeling of Dual-Material Triple-Gate Silicon-on-Nothing MOSFET
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2016.2643688
Abstract: A 3-D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET is proposed in this paper. 3-D Poisson’s equation with proper boundary conditions was solved to obtain the surface potential variation of the… read more here.
Keywords: gate silicon; silicon nothing; triple gate; material triple ... See more keywords
A Split Triple-Gate Power LDMOS With Improved Static-State and Switching Performance
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2910126
Abstract: A novel split triple-gate (STG) LDMOS is proposed to improve static-state and switching performances. The proposed structure features a triple-gate and split gates (SGs). The triple-gate consists of planar part and trench part, and the… read more here.
Keywords: triple gate; tex math; gate; inline formula ... See more keywords
Upgrade of Drain Current Compact Model for Nanoscale Triple-Gate Junctionless Transistors to Continuous and Symmetric
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2937159
Abstract: In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our… read more here.
Keywords: compact model; triple gate; current compact; drain current ... See more keywords