Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch
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DOI: 10.1109/access.2021.3104335
Abstract: Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes… read more here.
Keywords: triple node; power; self recoverable; delay ... See more keywords
Radiation Hardened Latch Designs for Double and Triple Node Upsets
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Emerging Topics in Computing"
DOI: 10.1109/tetc.2017.2776285
Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,… read more here.
Keywords: dnu tolerant; tolerant latch; triple node; node upsets ... See more keywords