High speed true random number generator with a new structure of coarse-tuning PDL in FPGA
Sign Up to like & getrecommendations! Published in 2018 at "Journal of Semiconductors"
DOI: 10.1088/1674-4926/39/3/035001
Abstract: A metastability-based TRNG (true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL (programmable delay line). With the proposed… read more here.
Keywords: number generator; coarse tuning; random number; tuning pdl ... See more keywords