A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3123827
Abstract: This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which… read more here.
Keywords: jitter; fractional type; type sampling; ghz fractional ... See more keywords
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc Reference Spur
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2023.3236309
Abstract: This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a… read more here.
Keywords: ghz type; reference; sampling pll; type sampling ... See more keywords
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3231536
Abstract: This brief reports a universal stability criterion for the type-I sampling phase-locked loop (S-PLL). The linear-time- variant model predicts with precision a maximum phase margin that decreases linearly with the increasing loop bandwidth (BW), leading… read more here.
Keywords: sampling phase; criterion type; universal stability; stability criterion ... See more keywords
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3229342
Abstract: This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase… read more here.
Keywords: differential parallel; double edge; series double; parallel series ... See more keywords
Unbiased Estimation of Population Mean Using Lahiri-Midzuno-Sen Type Sampling Scheme
Sign Up to like & getrecommendations! Published in 2020 at "Artificial Intelligence Review"
DOI: 10.9734/air/2020/v21i630209
Abstract: This paper considers the problem of estimating the population mean under double sampling. We have suggested the generalized class of estimators under Lahiri (1951) to Midzuno (1952) and Sen (1952) type sampling scheme and its… read more here.
Keywords: sampling scheme; sen; population mean; midzuno ... See more keywords