Improving the performance of dual-k spacer underlap Double Gate TFET
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DOI: 10.1016/j.spmi.2018.10.006
Abstract: Abstract In this paper, the effect of dual-k spacer is investigated on underlap Double-Gate TFET (DGTFET) for low-k and high-k gate dielectrics. Simulation study shows that the position of dual-k spacer junction must be aligned… read more here.
Keywords: double gate; gate; dual spacer; underlap double ... See more keywords