Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
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DOI: 10.1109/tcad.2018.2837103
Abstract: Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide… read more here.
Keywords: validation debug; error detection; validation; hardware accelerators ... See more keywords