Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals
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DOI: 10.1109/tcsii.2025.3578208
Abstract: Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors.… read more here.
Keywords: clock jitter; vco adcs; clock; adcs presence ... See more keywords