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Published in 2024 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2024.3458463
Abstract: This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub- $\mu $ s locking time when synthesizing millimeter-wave (mm-wave) frequencies. The proposed function-reused (FR) voltage-controlled oscillator (VCO)-buffer eliminates…
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Keywords:
sub sampling;
fll;
jitter;
vco buffer ... See more keywords