Surface residual stress in amorphous SiO2 insulating layer on Si substrate near a Cu through-silicon via (TSV) investigated by nanoindentation
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DOI: 10.1016/j.mssp.2021.106153
Abstract: Abstract Thermomechanical reliability remains challenging in through-silicon via (TSV) manufacture, a key technology in three-dimensional packaging of integrated circuits. A primary issue in reliability is the residual stress created during manufacture and operation by mismatch… read more here.
Keywords: silicon via; stress amorphous; residual stress; via tsv ... See more keywords