High performance suspended spiral inductor and band-pass filter by wafer level packaging technology
Sign Up to like & getrecommendations! Published in 2017 at "Microsystem Technologies"
DOI: 10.1007/s00542-016-2977-1
Abstract: Suspended inductors and 2.45 GHz BPF with patterned ground shields on the lossy silicon substrate by using Cu/BCB based wafer level packaging and bulk Si etching technologies were fabricated. Thick BCB interlayer is used as the… read more here.
Keywords: wafer level; level packaging; band; pass ... See more keywords
Wafer-level vacuum-encapsulated rate gyroscope with high quality factor in a commercial MEMS process
Sign Up to like & getrecommendations! Published in 2017 at "Microsystem Technologies"
DOI: 10.1007/s00542-016-3250-3
Abstract: We report the design and fabrication of a rate gyroscope sensor that is characterized by a high quality factor (52,300), unmatched resonance mode and low noise performance. The gyroscope dimensions are 1800 µm × 850 µm with 30 µm device… read more here.
Keywords: gyroscope; wafer level; high quality; quality factor ... See more keywords
Wafer-level micropackaging in thin film technology for RF MEMS applications
Sign Up to like & getrecommendations! Published in 2018 at "Microsystem Technologies"
DOI: 10.1007/s00542-017-3583-6
Abstract: In this work, a thin-film packaging was developed to be used for radio-frequency microelectromechanical system configurations. The fabricated packages are suspended membranes in the multilayer SixNy/aSi/SixNy on conductive coplanar waveguides (CPWs) of different length. Several… read more here.
Keywords: wafer level; film technology; level micropackaging; thin film ... See more keywords
Wafer-level vacuum package of two-dimensional micro-scanner
Sign Up to like & getrecommendations! Published in 2018 at "Microsystem Technologies"
DOI: 10.1007/s00542-017-3668-2
Abstract: We present wafer-level vacuum package of two-dimensional (2-D) micro-scanner based on glass-silicon anodic bonding. To form the sacrificial gap for evacuating air in the package cavity before hermetically sealed, the reflow process of Au/Sn/Cr posts… read more here.
Keywords: package; wafer level; scanner; vacuum ... See more keywords
Wafer Level Solid Liquid Interdiffusion Bonding: Formation and Evolution of Microstructures
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Electronic Materials"
DOI: 10.1007/s11664-020-08530-y
Abstract: Wafer-level solid liquid interdiffusion (SLID) bonding, also known as transient liquid-phase bonding, is becoming an increasingly attractive method for industrial usage since it can provide simultaneous formation of electrical interconnections and hermetic encapsulation for microelectromechanical… read more here.
Keywords: wafer level; liquid interdiffusion; formation; level solid ... See more keywords
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
Sign Up to like & getrecommendations! Published in 2018 at "Solid-state Electronics"
DOI: 10.1016/j.sse.2018.04.001
Abstract: Abstract This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on… read more here.
Keywords: wafer level; variability soi; variability; process ... See more keywords
Wafer-level fabrication of individual solid-state nanopores for sensing single DNAs.
Sign Up to like & getrecommendations! Published in 2020 at "Nanotechnology"
DOI: 10.1088/1361-6528/ab9474
Abstract: For biomolecule sensing purposes a solid-state nanopore platform based on silicon has certain advantages as compared to nanopores on other substrates such as graphene, silicon nitride, silicon oxide etc. Capitalizing on the developed CMOS technology,… read more here.
Keywords: solid state; state; wafer level; level fabrication ... See more keywords
Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Access"
DOI: 10.1109/access.2020.3034321
Abstract: In this article, accurate physical and SPCIE model of wafer-level monolayer molybdenum disulfide (MoS2) device are developed to guide the devices and circuits design, which is the foundation of high-performance analog chip design. Moreover, the… read more here.
Keywords: analog integrated; spice model; mos2; model ... See more keywords
Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/ectc.2017.309
Abstract: In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip… read more here.
Keywords: wafer level; level packaging; warpage thermal; warpage ... See more keywords
Wafer-Level Characterization of Silicon Nitride CWDM (De)Multiplexers Using Bayesian Inference
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Photonics Technology Letters"
DOI: 10.1109/lpt.2020.3004850
Abstract: A cascaded Mach-Zehnder interferometer based filter for coarse wavelength (de)multiplexing (CWDM) at the O-band is fabricated and tested on a silicon nitride on SOI platform. We characterize the chip-to-chip performance variability of the filter devices… read more here.
Keywords: bayesian inference; wafer level; silicon nitride; level characterization ... See more keywords
Viscoelastic Warpage Modeling of Fan-Out Wafer-Level Packaging During Wafer-Level Mold Cure Process
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2020.2992041
Abstract: This article aims to characterize the warpage evolution of fan-out wafer-level packaging (FOWLP) during the wafer-level mold cure process. A finite-element analysis (FEA)-based process modeling framework, which includes the effects of geometric nonlinearity, gravity, and… read more here.
Keywords: warpage; process; fan wafer; cure ... See more keywords