Next-generation ferroelectric domain-wall memories: principle and architecture
Sign Up to like & getrecommendations! Published in 2019 at "NPG Asia Materials"
DOI: 10.1038/s41427-018-0102-x
Abstract: The downscaling of commercial one-transistor–one capacitor ferroelectric memory cells is limited by the available signal window for the use of a charge integration readout technique. However, the erasable conducting charged walls that occur in insulating… read more here.
Keywords: wall memories; ferroelectric domain; domain wall; next generation ... See more keywords
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2022.3188206
Abstract: Spintronic domain-wall memories (DWMs) offer improved memory density and energy compared to conventional memories, but are susceptible to shifting faults. We propose PIETT (Pinning, Insertion, Erasure, and Translation-fault Tolerance) for improved misalignment correction versus the… read more here.
Keywords: domain wall; misalignment; fault; pinning faults ... See more keywords