A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2016.2632300
Abstract: A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid… read more here.
Keywords: adc; pam4 wireline; time; time interleaved ... See more keywords
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2020.3024261
Abstract: A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based… read more here.
Keywords: time interleaved; front end; inverter based; way time ... See more keywords