Optimization of thermal aware multilevel routing for 3D IC
Sign Up to like & getrecommendations! Published in 2019 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-019-01513-y
Abstract: Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased… read more here.
Keywords: aware multilevel; wire length; optimization thermal; wire ... See more keywords
Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs
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DOI: 10.1109/tetc.2016.2630064
Abstract: Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption… read more here.
Keywords: multi tier; integration; methodology; wire length ... See more keywords