Articles with "wire planning" as a keyword



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Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing

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Published in 2017 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"

DOI: 10.1109/tvlsi.2016.2600681

Abstract: Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even… read more here.

Keywords: self aligned; cut mask; wire planning;