A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
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DOI: 10.1109/jssc.2016.2632300
Abstract: A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid… read more here.
Keywords: adc; pam4 wireline; time; time interleaved ... See more keywords