Aging-aware scheduling and binding in high-level synthesis considering workload effects
Sign Up to like & getrecommendations! Published in 2020 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2019.113549
Abstract: Abstract Transistor aging is a major reliability concern in nanoscale digital design, and addressing it during high-level synthesis (HLS) is essential to enhance the lifetime of circuits. Motivated by exploring workload effects on aging, we… read more here.
Keywords: workload effects; effects aging; high level; level synthesis ... See more keywords