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Published in 2018 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2017.2706561
Abstract: On-chip communication system design starting from a high-level model can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing its quality-of-service (QoS) property, in our context, per-flow delay bound, is…
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Keywords:
methodology;
xmas;
analysis;
analysis methodology ... See more keywords